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1 memory ics 8k 8 bit sram BR6265BF-N10SL the BR6265BF-N10SL is an 8192 word 8 bit cmos static ram. it runs on a 5v single power supply, and input can be directed coupled with ttl. current dissipation in the non-selected state is extremely low at 20 m a (max.), and memory information can be retained even at a low voltage of 2v, making this product ideal for battery backup opera- tions. both the access and cycle timing are 100ns, facilitating timing design. applications general-purpose block diagram 65536bit (128 512) memory cell array row decorder row address buffer input data control column switch column decoder control column address buffer control buffer ce1 ce2 we a8 a5 a6 a7 a12 a9 a11 a 1a 2a 3a 4 a 0 a 1 0 i / o 0 i / o 7 oe output data features 1) sram with an 8192 8 bit configuration. 2) 5v single power supply voltage with 10% fluctua- tion tolerance. 3) high speed access time of 100ns. 4) ttl compatible input / output. 5) input and output use the same pin, and there are 3 output states. 6) no clock is necessary (asynchronous static circuit). 7) input and output data are in the same phase. 8) low power dissipation.
2 memory ics BR6265BF-N10SL absolute maximum ratings (ta = 25?) parameter symbol limits unit v cc ? 0.5 * 1 ~ + 7.0 v pd 850 * 2 mw topr ? 55 ~ + 125 c tstg 0 ~ 70 c v i ? 0.5 ~ v cc + 0.5 v * 1 at pulse width of 50 ns : 3.0v ( min. ) power supply voltage power dissipation operating temperature storage temperature i / o voltage * 2 reduced by 8.5mw for each increase in ta of 1 c over 25 c. recommended operating conditions (ta = 25?) parameter symbol min. typ. max. unit v cc 4.5 5.0 5.5 v v ih 2.2 v cc + 0.5 v v il ? 0.3 0.8 v ta 0 70 c power supply voltage input high level voltage ambient temperature input low level voltage pin descriptions 1nc i / o0 ~ i / o7 15 ~ 19 ce1 20 ce2 26 oe 22 we 27 v cc 28 14 v ss a0 ~ a12 23 ~ 25 2 ~ 10, 21, pin no. 11 ~ 13, pin name internal chip and not connected 8192-byte memory address input chip enable control input chip enable control input output enable control input write enable control input 5v 10 % power supply reference voltage for all input / output, 0v 8-bit data i / o function
3 memory ics BR6265BF-N10SL electrical characteristics (unless otherwise noted, ta = 0 to 70?, v cc = 5v 10%) parameter min. typ. unit measurement circuit ? 0.3 * 1 0.8 v 2.2 v 0 0.4 v 2.4 v v 1 m a 1 m a 40 ma 10 ma f = 1mhz 3ma 20 m a 20 m a ce2 % 0.2v v il v ih v ol v oh i li i lo i cca1 i cca2 i sb i sb1 i sb2 v cc ce1 = v ih or ce2 = v il v out = 0 ~ v cc v in = 0 ~ v cc i oh = ? 0.1ma i oh = ? 1.0ma i ol = 2.1ma symbol max. conditions v cc 0.8 v cc fig.1 fig.2 fig.3 fig.4 fig.5 fig.5 fig.6 ce1 ^ v cc ? 0.2v, ce2 ^ v cc ? 0.2v or ce2 % 0.2v v cc + 0.5 ce1 = v il , ce2 = v ih , i / o: open ce1 = v il , ce2 = v ih , i / o: open input leakage current output leakage current average operating current standby current input low level voltage input high level voltage output low level voltage output high level voltage * 1 at input voltage pulse width of 50 ns or less : ? 3.0v minimum cycle time
4 memory ics BR6265BF-N10SL measurement circuits v v cc 2.1ma v ol v ss v cc i / o0 ~ i / o7 data sets all output to low (data 00) fig. 1 output low level voltage measurement circuit v v cc 1.0ma v oh v ss v cc i / o0 ~ i / o7 data sets all output to high (data ff) fig. 2 output high level voltage measurement circuit a v cc v ss v cc v in = 0 ~ v cc a0 ~ a12 ce1, ce2 i l1 fig. 3 input leakage measurement circuit a v cc v cc v ss v cc v out = 0 ~ v cc i / o0 ~ i / o7 oe i lo fig. 4 output leakage current measurement circuit a open q w sw v il or v ih (min. cycle) v il or v ih (1mhz cycle) v cc v cc v ih v il i cca1 , i cca2 i / o0 ~ i / o7 a0 ~ a12 v ss we ce2 ce1 oe q : average operating current icca1 w : average operating current icca2 fig. 5 current dissipation measurement circuit a open v cc v cc or gnd v cc i sb , 1 i / o0 ~ i / o7 a0 ~ a12 v ss ce2 ce1 v ih fig. 6 standby current measurement circuit
5 memory ics BR6265BF-N10SL operating modes control pin oe ce1 ce2 we xhxx xxlx hlhh llhh xlhl i / o x : either v il or v ih mode wait state wait state output disabled read write high impedance high impedance high impedance data output data output power dissipation standby state standby state operating state operating state operating state read cycle parameter symbol min. max. unit 100 ns 100 ns 100 ns 100 ns 40 ns 10 ns 10 ns 10 ns 5 ns 35 ns 35 ns 35 ns t rc t aa t co1 t co2 t oe t oh t lz1 t lz2 t olz t hz1 t hz2 t ohz read cycle time address access time output hold time ce1 output set time ce2 output set time ce1 access time ce2 access time oe access time oe output reset time ce1 deselect output floating ce2 deselect output floating oe disable output floating ac test conditions (ta = 0 to 70?, v cc = 5v 10%) input pulse level : 0.8 to 2.4v input rise / fall time : 5ns i / o timing level : 1.5v output load : 1 ttl gate and cl = 100pf
6 memory ics BR6265BF-N10SL read cycle timing chart 1 (ce1 = oe = v il , ce2 = we = v ih ) dout address t rc t aa t oh previous valid data valid data fig.7 read cycle timing chart 2 (we = v ih ) dout oe ce1 ce2 address t rc t aa t co1 t lz1 t co2 t lz2 t oe t olz valid data t ohz t hz1 t hz2 high impedance fgi.8
7 memory ics BR6265BF-N10SL write cycle symbol min. max. unit 100 ns 80 ns 80 ns 0 ns 60 ns 0 ns 0 ns 35 ns 40 ns 0 ns 5 ns t wc t cw t aw t as t wp t wr t wr1 t whz t dw t dh t ow parameter write cycle time chip select time address valid time address setup time write pulse width input data set time input data hold time ce1, ce2 output delay time we output delay time we ?output floating time we ?output set time write cycle timing chart 1 (we control) high impedance t wc t aw t wr t cw t cw t wp t as t dw t dh t whz t ow valid data address oe we d in d out ce1 ce2 fig.9
8 memory ics BR6265BF-N10SL write cycle timing chart 2 (ce1 control) t aw t wc address oe d in d out we ce1 ce2 valid data t dw t whz t lz1 t dh t wp t cw t as t wr1 fig.10
9 memory ics BR6265BF-N10SL write cycle timing chart 3 (ce2 control) valid data t dw t whz t lz2 t dh t wp t cw t aw t wc t as t wr1 address oe we d in d out ce1 ce2 fig.11 * while the i / o pin is in output state, input signals should not be applled which are in reverse phase to the output. * the contents noted in this document may fall under the jurisdiction of services pertaining to overseas exchange rates and overseas control regulations (services pertaining to design, construction, specifications), and may requlre special handiing.
10 memory ics BR6265BF-N10SL data retention characteristics at low power supply voltage (ta = 0 to 70?): sl version products parameter symbol min. typ. max. unit 2.0 5.5 v 10 m a 0 ns 5 ms or ce2 % 0.2v v dr t cdr t r conditions ce1 ^ v cc ? 0.2v, ce2 ^ v cc ? 0.2v or ce2 % 0.2v, v cc = 3.0v i ccdr * ce1 ^ v cc ? 0.2v, ce2 ^ v cc ? 0.2v supply voltage data retention current cs data retention time operating recovery time data retention power * 1 m a (max.), when ta = 0 ~ 40 c data retention waveform at low power supply voltage v cc ce1 v cc ce2 0.4v 0.4v 2.2v 2.2v 4.5v 4.5v 4.5v 4.5v data retention mode data retention mode v dr v dr ce2 % 0.2v ce1 ^ v dr ?0.2v t cdr t r t cdr t r fig.12
11 memory ics BR6265BF-N10SL external dimensions (units: mm) 18.0 0.2 8.4 0.2 11.8 0.3 2.55 0.10 0.20 1.27 28 15 14 1 0.40 0.10 0.5min. 0.15 0.1 0.10 sop-n28

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